Certain conventional CCD imagers employ an on-chip amplifier circuit which follows a charge detection node to convert the sensed charge to an output voltage signal. These conventional designs have a CCD serial register that terminates in a detection node usually represented by a detection capacitor. The detection capacitor is in turn coupled to the first transistor of a dual source follower circuit, the sources of which are biased by constant current sources. The dual source followers serve as a buffer of the voltage that appears on the detection capacitor as a result of the charge sensed at the node and provide sufficient driving capacity for the off-chip circuitry with no additional voltage gain.
In certain applications, such as image sensors for medical endoscopes, the CCD image sensor is required to be very small, with a very small charge to be detected. The rest of the supporting circuits must be remotely located from the sensor. In applications such as these, it is desirable to first amplify and then buffer the signal on-chip to prevent interference picked up from long leads to the remotely located processing circuits.
In view of the small size of the on-chip circuits, and small available charge quantity, it is also desirable to increase the charge/voltage conversion gain. This is conventionally performed by making the capacitance of the detection capacitor as low as possible. The first transistor of the conventional dual source follower must also be made to be as small as possible to reduce its input capacitance C.sub.i. A small first transistor, however, implies a large 1/f noise, i.e. a source of noise that is inversely proportional to the signal frequency. The value of the 1/f noise associated with the first transistor is inversely proportional to the gate area.
In conventional CCD imagers, on-chip gain amplifiers are usually not used. This is because the requirements for such on-chip gain amplifiers are very stringent and difficult to satisfy without overall performance degradation.
In general, a small, on-chip gain amplifier must meet the following requirements for amplifying a CCD video signal in a satisfactory manner. First, it must produce a signal gain in the range of three to five without amplification of the CCD transfer clock feedthrough signal. In CCD devices, the signal representing the amount of radiation sensed by the cell is comparable to or much smaller than the clock feedthrough signal. It is therefore necessary to amplify only the signal and not the clock feedthrough.
Second, the amplifier should have a low power consumption, with current on the order of 0.5 to 1.5 milliamperes. This is because a large power drain would generate excessive device heating and would therefore increase dark current.
Third, the amplifier must have a high frequency response. The amplifier must pass high frequencies to eliminate distortions from the clock/video waveform. Typical clock frequencies range from 1 megahertz to 10 megahertz at present, and may range up to 50 megahertz in future high density television (HDTV) applications.
Fourth, the amplifier must have a low noise so that the actual signal, which will have a relatively small amplitude, will not be lost.
Fifth, the gain of the amplifier must be fixed and must be independent of temperature and power supply variations.
Sixth, the amplifier performance must be insensitive to process variations. In particular, the location of the amplifier on-chip makes it impossible to externally adjust the amplifier bias point. Therefore, this must be provided automatically.
Seventh, it is desirable that the polarity of the amplifier output be selectable between inverting and non-inverting.
Finally, the amplifier circuit components must be compatible with the virtual phase CCD process to avoid unnecessary process complications and added manufacturing cost.